Socket, and test apparatus and method using the socket

ABSTRACT

An apparatus for testing electric characteristics of a test object including first connection terminals on a bottom surface and second connection terminals on a top surface, the apparatus comprises a test board comprising first pads on a predetermined surface; a socket configured to electrically connect the test object to the test board; and a handler configured to transport the test object to the socket. The socket comprises a first connection unit configured to be electrically connected to the first connection terminals of the test object and a second connection unit configured to be electrically connected to the second connection terminals of the test object.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 12/215,769, filed on Jun. 30, 2008, which claims the benefit ofKorean patent application number 10-2007-0069259, filed on Jul. 10,2007, in the Korean Intellectual Property Office, the contents of whichapplications are incorporated herein in their entirety by reference.

FIELD OF THE INVENTION

The present invention disclosed herein relates to a test apparatus andmethod, and more particularly, to an apparatus and method for testingelectrical characteristics of a semiconductor device package.

BACKGROUND

In semiconductor industries, packaging technology has been advanced forincreasing reliability in packaging and mounting small-sized integratedsemiconductor chips. For example, demands for miniaturization haveaccelerated the development of small packages having sizes close to thesizes of integrated semiconductor chips, and demands for reliablemounting technology have spurred the development of packaging technologyfor efficiently packaging semiconductor chips and improving mechanicaland electrical characteristics of the packaged semiconductor chips.

In addition, various technologies have been developed to providehigh-capacity semiconductor products and satisfy the demands forsmall-sized, high-performance electric/electronic products. For example,high-capacity semiconductor products can be fabricated using highlyintegrated memory chips (i.e., high-capacity memory chips). Highlyintegrated memory chips can be fabricated by integrating a larger numberof cells into a given region of the memory chip.

However, it is difficult and takes a large amount of time to develophighly integrated memory chips. For example, it is necessary to developfine pattern forming technology for highly integrated memory chips.However, it is difficult and takes a large amount of time to develop thefine pattern forming technology. Accordingly, stacking technology hasbeen developed as another way of providing high capacity semiconductorproducts. According to the stacking technology, at least twosemiconductor chips or semiconductor device packages are verticallystacked for providing high-capacity semiconductor products. For example,a 128-M memory chip can be fabricated by stacking two 64-M memory chips,and a 256-M memory chip can be fabricated by stacking two 128-M memorychips. In addition to the increase of storage capacity, semiconductordevice packages can be mounted more densely and efficiently by using thestacking technology.

In general, a stack type (sometimes referred to as a “multi-chip”)semiconductor device package includes a first semiconductor devicepackage and a second semiconductor device package. Connection terminals,such as a ball grid array (BGA), are disposed on a bottom surface of thefirst semiconductor device package for electrically connecting the firstsemiconductor device package to an external circuit, such as a circuitformed on a system substrate, and connection terminals, such as pads,are disposed on a top surface of the first semiconductor device packagefor electrically connecting the first semiconductor device package tothe second semiconductor device package. In addition, connectionterminals, such as pads, are also disposed on a bottom surface of thesecond semiconductor device package for electrically connecting thesecond semiconductor device package to the first semiconductor devicepackage. Solder balls can be disposed between the connection terminalsof the first and second semiconductor device packages for electricallyconnecting the first and second semiconductor device packages.

Electric characteristics, such as electrical connection states of theconnection terminals of the first semiconductor device package, can betested as follows. First, the electric characteristics of the connectionterminals disposed on the bottom surface of the first semiconductordevice package are tested using a test apparatus. Then, if it isdetermined that the electric characteristics of the connection terminalsof the bottom surface of the first semiconductor device package areallowable, the electric characteristics of the connection terminalsdisposed on the top surface of the first semiconductor device packageare tested. In detail, after connecting the second semiconductor devicepackage to the first semiconductor device package using solder balls,the electric characteristics of the connection terminals of the topsurface of the first semiconductor device package are tested by applyinga signal to the second semiconductor device package through theconnection terminals of the top surface of the first semiconductordevice package and evaluating the operation state of the secondsemiconductor device package using the applied signal.

However, the above method takes a large amount of time to test all theconnection terminals of the top and bottom surfaces of the firstsemiconductor device package.

Moreover, even if the second semiconductor device package is notdefective, the second semiconductor device package can be discarded ifit is determined that the electric characteristics of the connectionterminals of the top surface of the first semiconductor device packageare not allowable, i.e., defective.

SUMMARY OF THE INVENTION

In accordance with the present invention, provided is an apparatus andmethod for efficiently testing electric characteristics of asemiconductor device package, such as electric connection states of thesemiconductor device package—including connection terminals on top andbottom surfaces thereof.

In accordance with the present invention, also provided is an apparatusand method for rapidly testing electric characteristics of asemiconductor package, such as electric connection states of asemiconductor device package—including connection terminals on top andbottom surfaces thereof.

In accordance with the present invention, also provided is an apparatusand method for testing electric connection states of a multi-chipsemiconductor device package that eliminates the possibility ofdiscarding a non-defective upper semiconductor device package accordingto the test result of a lower semiconductor device package.

Additional features and advantages of the invention will be set forth inthe description which follows, and in part will be apparent from thedescription, or can be learned by practice of the invention.

In accordance with one aspect of the present invention, provided is anapparatus for testing electric characteristics of a test objectincluding first connection terminals on a bottom surface and secondconnection terminals on a top surface. The apparatus includes a testboard including first pads on a predetermined surface, a socketconfigured to electrically connect the test object to the test board,and a handler configured to transport the test object to the socket. Thesocket includes a first connection unit configured to electricallyconnect to the first connection terminals of the test object, and asecond connection unit configured to electrically connect to the secondconnection terminals of the test object.

The first connection unit can include first pins configured toelectrically connect the first pads of the test board to the firstconnection terminals of the test object. And the second connection unitcan include: a socket substrate including first pads and second padselectrically connected together; second pins configured to electricallyconnect the first pads of the socket substrate to the second connectionterminals of the test object; and a reference electronic deviceconfigured to electrically connect to the second pads of the socketsubstrate and to exchange electric signals with the test object.

The socket can further include: a first body; and a second bodyconfigured to detachably couple to the first body, wherein the firstpins of the first connection unit are disposed in first holes formedvertically through the first body, the second pins of the secondconnection unit are disposed in second holes formed vertically throughthe second body, and the socket substrate is disposed at a top portionof the second body.

A recess can be formed in a top surface of the first body or a bottomsurface of the second body for receiving the test object.

The socket substrate and the second body can be fixed to the handler.

An alignment pin can be disposed on one of the first body and the secondbody, and an alignment hole can be formed in the other of the first bodyand the second body for receiving the alignment pin.

The apparatus can further include a support configured to fix the firstbody to the test board and having an opening formed therein forreceiving the first body, wherein an alignment pin can be disposed onone of the support and the handler, and an alignment hole can be formedin the other of the support and the handler and configured to receivethe alignment pin.

The reference electronic device can be soldered to the socket substrate.

The reference electronic device can be detachably attached to the socketsubstrate.

The test object can be a package in which a first semiconductor deviceis packaged, and the reference electronic device can include a secondsemiconductor device configured to exchange electric signals with thefirst semiconductor device.

The test object can be a first semiconductor device package in which afirst semiconductor device is packaged, and the reference electronicdevice can include a second semiconductor device of a secondsemiconductor device package to be stacked on the first semiconductordevice package.

The first semiconductor device can include a logic chip, and the secondsemiconductor device can include a memory chip.

The test board can further include second pads, and the first connectionunit can include first pins configured to electrically connect the firstpads of the test board to the first connection terminals of the testobject. And the second connection unit can include: a socket substrateincluding first pads and second pads electrically connected together;second pins configured to electrically connect the first pads of thesocket substrate to the second connection terminals of the test object;and third pins configured to electrically connect the second pads of thesocket substrate to the second pads of the test board.

The socket can further include: a first body including first holesformed vertically through the first body and configured to receive thefirst pins of the first connection unit; and a second body includingsecond holes formed vertically through the second body and configured toreceive the second pins of the second connection unit, wherein a recessis formed in a top surface of the first body or a bottom surface of thesecond body and configured to receive the test object, and third holesare formed in one of the first and second bodies in which the recess isformed, the third holes being located outside the recess and configuredto receive the third pins of the second connection unit.

The socket substrate and the second body can be fixed to the handler.

An alignment pin can be disposed on one of the first body and the secondbody, and an alignment hole can be formed in the other of the first bodyand the second body and configured to receive the alignment pin.

The apparatus can further include a support configured to fix the firstbody to the test board and having an opening formed therein forreceiving the first body, wherein an alignment pin can be disposed onone of the first body and the second body, and an alignment hole can beformed in the other of the first body and the second body for receivingthe alignment pin.

The test object can be a semiconductor device package.

In accordance with another aspect of the present invention, provided isa socket for use in an apparatus for testing electric characteristics ofa test object. The socket includes: a housing configured to receive thetest object; a first connection unit configured to be electricallyconnected to first connection terminals disposed on a bottom surface ofthe test object when the test object is placed in the housing; and asecond connection unit configured to be electrically connected to secondconnection terminals disposed on a top surface of the test object whenthe test object is placed in the housing.

The housing can include: a first body; and a second body configured todetachably couple to the first body, wherein the first connection unitcan include first pins inserted in vertical holes formed through thefirst body, wherein the second connection unit can include: a socketsubstrate including first pads and second pads electrically connectedtogether; second pins configured to electrically connect the first padsof the socket substrate to the second connection terminals of the testobject; and a reference electronic device configured to electricallyconnect to the second pads of the socket substrate and to exchangeelectric signals with the test object.

In the socket a recess can be formed in a top surface of the first bodyor a bottom surface of the second body and configured to receive thetest object.

An alignment pin can be disposed on one of the first body and the secondbody, and an alignment hole can be formed in the other of the first bodyand the second body and configured to receive the alignment pin.

The housing can include: a first body; and a second body configured todetachably couple to the first body, wherein the first connection unitcan include first pins inserted in first holes formed vertically throughthe first body, wherein the second connection unit can include: a socketsubstrate including first pads and second pads electrically connectedtogether; second pins inserted in second holes formed vertically throughthe second body and configured to electrically connect the first pads ofthe socket substrate to the second connection terminals of the testobject; and third pins inserted in third holes formed in one of thefirst body and the second body and configured to electrically connect tothe second pads of the socket substrate.

A recess can be formed in one of the first and second bodies andconfigured to receive the test object, and the other of the first andsecond bodies can be inserted in the recess when the test object istested.

An alignment pin can be disposed on one of the first body and the secondbody, and an alignment hole can be formed in the other of the first bodyand the second body and configured to receive the alignment pin.

In accordance with still another aspect of the present invention, thereis provided a method of testing electric characteristics of a testobject including first connection terminals on a bottom surface andsecond connection terminals on a top surface. The method includes:providing a socket and loading the test object in the socket, the sockethaving first pins electrically contacting the first connection terminalsof the test object and second pins electrically contacting the secondconnection terminals of the test object. The method further includesapplying an electric signal from a test board to the first pins tosimultaneously test electric characteristics of the first and secondconnection terminals of the test object.

The method can further include electrically connecting the second pinsof the socket to an electronic device using a socket substrate thatallows the electronic device to exchange electric signals with the testobject, including transmitting the electric signal output from the testboard back to the test board through the first pins, the test object,the second pins, the socket substrate, the electronic device, the socketsubstrate, the second pins, the test object, and the first pins.

The test object can be a semiconductor device package in which a firstsemiconductor device is packaged, and the electronic device can comprisea second semiconductor device exchanging electric signals with the firstsemiconductor device.

The test object can be a first semiconductor device package in which afirst semiconductor device is packaged, and the electronic device cancomprise a second semiconductor device of a second semiconductor devicepackage to be stacked on the first semiconductor device package.

The first semiconductor device can comprise a logic chip, and the secondsemiconductor device can comprise a memory chip.

The method can further include providing third pins contacting the testboard, and a socket substrate electrically connecting the second pinsand the third pins, including transmitting the electric signal outputfrom the test board back to the test board through the first pins, thetest object, the second pins, the socket substrate, and the third pins.

The test object can be a semiconductor device package.

The test object can be one of a plurality of semiconductor devicepackages included in a multi-chip semiconductor device package.

BRIEF DESCRIPTION OF THE FIGURES

The accompanying figures are included to provide a further understandingof the present invention, and are incorporated in and constitute a partof this specification. The drawings illustrate exemplary embodiments ofdevices and methods in accordance with aspects of the present inventionand, together with the description, serve to explain principles of thepresent invention. In the figures:

FIG. 1 is a schematic cross-sectional view illustrating an embodiment ofa multi-chip semiconductor device package according to an aspect of thepresent invention;

FIG. 2 is an exploded cross-sectional view illustrating a firstembodiment of a test apparatus according to an aspect of the presentinvention;

FIG. 3 is a cross-sectional view illustrating the test apparatus of FIG.2 assembled for testing a semiconductor device package loaded therein;

FIG. 4 is a cross-sectional view illustrating an embodiment of amodified version of the test apparatus depicted in FIG. 3;

FIG. 5 is an exploded cross-sectional view illustrating a secondembodiment of a test apparatus according to another aspect of thepresent invention;

FIG. 6 is a cross-sectional view illustrating the test apparatus of FIG.5 assembled for testing a semiconductor device package loaded therein;and

FIG. 7 is a cross-sectional view illustrating an embodiment of amodified version of the test apparatus depicted in FIG. 6.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments in accordance with aspects of the presentinvention will be described below in more detail with reference to FIGS.1 through 7. The present invention can, however, be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. In the figures, the dimensions of layersand regions are exaggerated for clarity of illustration. Descriptions ofwell-known elements may be omitted for conciseness.

It will be understood that, although the terms first, second, etc. arebe used herein to describe various elements, these elements should notbe limited by these terms. These terms are used to distinguish oneelement from another, but not to imply a required sequence of elements.For example, a first element can be termed a second element, and,similarly, a second element can be termed a first element, withoutdeparting from the scope of the present invention. As used herein, theterm “and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that when an element is referred to as being “on”or “connected” or “coupled” to another element, it can be directly on orconnected or coupled to the other element or intervening elements can bepresent. In contrast, when an element is referred to as being “directlyon” or “directly connected” or “directly coupled” to another element,there are no intervening elements present. Other words used to describethe relationship between elements should be interpreted in a likefashion (e.g., “between” versus “directly between,” “adjacent” versus“directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises,”“comprising,” “includes” and/or “including,” when used herein, specifythe presence of stated features, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, steps, operations, elements, components, and/or groupsthereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like may be used to describe an element and/or feature'srelationship to another element(s) and/or feature(s) as, for example,illustrated in the figures. It will be understood that the spatiallyrelative terms are intended to encompass different orientations of thedevice in use and/or operation in addition to the orientation depictedin the figures. For example, if the device in the figures is turnedover, elements described as “below” and/or “beneath” other elements orfeatures would then be oriented “above” the other elements or features.The device may be otherwise oriented (e.g., rotated 90 degrees or atother orientations) and the spatially relative descriptors used hereininterpreted accordingly.

In the following descriptions of preferred embodiments, test apparatusesand test methods are explained using a lower semiconductor devicepackage of a multi-chip semiconductor device package as a test object.However, the present invention is not limited to the lower semiconductordevice package. That is, the present invention can be used to testvarious electronic components having connection terminals on top andbottom surfaces.

FIG. 1 is a schematic cross-sectional view illustrating en embodiment ofa multi-chip semiconductor device package 1 according to an aspect ofthe present invention. Referring to FIG. 1, the multi-chip semiconductordevice package 1 includes a first semiconductor device package 10 and asecond semiconductor device package 20 disposed above the firstsemiconductor device package 10. The first semiconductor device package10 includes a first semiconductor device 12 and a substrate 13. Firstconnection terminals 14 are disposed on a bottom surface of the firstsemiconductor device package 10 for electrically connecting themulti-chip semiconductor device package 1 to an external circuit member,such as a system substrate, and second connection terminals 16 aredisposed on a top surface of the first semiconductor device package 10for electrically connecting the first semiconductor device package 10 tothe second semiconductor device package 20. The first connectionterminals 14 can have a ball shape like a ball gray array (BGA), and theconnection terminals 16 can have a pad shape.

The semiconductor device package 20 includes a second semiconductordevice 22 and a substrate 23. Connection terminals 24 are disposed on abottom surface of the semiconductor device package 20 for electricallyconnecting the semiconductor device package 20 to the firstsemiconductor device package 10. The first semiconductor device package10 and the semiconductor device package 20 are connected through solderballs 30 in this embodiment.

For example, the first semiconductor device 12 can include a logic chip,and the semiconductor device 22 can include a memory chip. In such acase, interconnection lines (not shown) can be formed on the substrate13 for electrically connecting the first and second connection terminals14 and 16 to the first semiconductor device 12. The memory chip can be adouble data rate (DDR) memory chip. However, as would be appreciated bythose skilled in the art having the benefit of this disclosure, thememory chip could be a different memory chip, such as a flash memorychip.

In the exemplary embodiments described below, the first semiconductordevice package 10 is described as a test target object, and testing ofelectric connection states or other characteristics of the first andsecond connection terminals 14 and 16 of the first semiconductor devicepackage 10 is explained.

FIG. 2 is an exploded cross-sectional view illustrating a firstembodiment of a test apparatus 2 according to an aspect of the presentinvention, FIG. 3 is a cross-sectional view illustrating the testapparatus 2 assembled for testing the first semiconductor device package10.

Referring to FIGS. 2 and 3, the test apparatus 2 includes a test unit100, a handler 200, and a socket 400. The test unit 100 applies an inputsignal to the first semiconductor device package 10 (hereinafter,referred to as a test object) and receives a signal output from the testobject 10 in response to the input signal. The test unit 100 evaluatesthe state of the test object 10 using the signal output from the testobject 10. The test unit 100 includes a test board 120. First pads 122are formed on a top surface of the test board 120. Automatic testequipment can be used as the test unit 100. The socket 400 electricallyconnects the first semiconductor device package 10 to the test board120. The handler 200 is configured to move the test object 10 to thesocket 400. The test unit 100 and the handler 200 have typicalstructures in this embodiment. Thus, detailed descriptions of the testunit 100 and handler 200 will be omitted here. The socket 400 is acharacteristic element of the test apparatus 2. In the followingdescription, the socket 400 will be mainly described in detail, andfeatures of the test unit 100 and handler 200 that differ from typicalstructures will be described.

The socket 400 includes a housing 420, a first connection unit 440, anda second connection unit 460. The housing 420 is disposed between thehandler 200 and the test board 120 and configured for receiving the testobject 10 during a test operation. The first connection unit 440 is usedto evaluate electrical connection states of the first connectionterminals 14 of the test object 10. The second connection unit 460 isused to evaluate electrical connection states of the connectionterminals 16 of the test object 10.

The first connection unit 440 includes a plurality of first pins 330 forelectrically connecting the first connection terminals 14 of the testobject 10 directly to the first pads 122 of the test board 120. Pogopins having elastic cores (not shown) can be used as the first pins 330.Ends of the first pins 330 are brought into contact with the firstconnection terminals 14 of the test object 10, respectively, and theother ends of the first pins 330 are brought into contact with the firstpads 122 of the test board 120, respectively.

The second connection unit 460 includes a socket substrate 360, secondpins 350, and a reference electronic device 380. The referenceelectronic device 380 is a semiconductor device capable of exchangingelectrical signals with the test object 10. In the current embodiment,the reference electronic device 380 can be the semiconductor devicepackage 20 to be stacked on the test object 10. Alternatively, thereference electronic device 380 can be the semiconductor device 22 ofthe semiconductor device package 20. The reference electronic device 380includes a memory chip. In a test operation, the memory chip iselectrically connected to the first semiconductor device 12 of the testobject 10.

The socket substrate 360 includes first pads 362 and second pads 364.Interconnection lines (not shown) are formed on the socket substrate 360for electrically connecting the first pads 362 and the second pads 364.The second pins 350 of the second connection unit 460 are used forelectrically connecting the first pads 362 of the socket substrate 360directly to the connection terminals 16 of the test object 10. Pogo pinshaving elastic cores (not shown) can be used as the second pins 350.Ends of the second pins 350 are brought into contact with the connectionterminals 16 of the test object 10, respectively, and the other ends ofthe second pins 350 are brought into contact with the first pads 362 ofthe socket substrate 360, respectively.

The reference electronic device 380 is mounted on the socket substrate360 and makes electric contact with the second pads 364 of the socketsubstrate 360. The reference electronic device 380 can be mounted on thesocket substrate 360 by soldering. In this case, the referenceelectronic device 380 can be reliably connected to the second pads 364of the socket substrate 360. Alternatively, the reference electronicdevice 380 can be detachably mounted on the socket substrate 360 usingfasteners, such as screws, for example. In this case, the referenceelectronic device 380 can be easily replaced.

Electrical connection states of the first and second connectionterminals 14 and 16 of the test object 10 can be tested using the testapparatus 2 as follows. For example, a signal output from the test board120 is transmitted to the reference electronic device 380 sequentiallythrough the first pins 330, the first connection terminals 14 of thetest object 10, the first semiconductor device 12 of the test object 10,the connection terminals 16, the second pins 350, and the socketsubstrate 360. Then, the signal is transmitted from the referenceelectronic device 380 back to the test board 120 through the socketsubstrate 360, the second pins 350, the connection terminals 16, thefirst semiconductor device 12 of the test object 10, the firstconnection terminals 14, and the first pins 330. The test unit 100evaluates connection states and other electric characteristics of thefirst and second connection terminals 14 and 16 of the test object 10using the signal returned from the reference electronic device 380.

Exemplary elements of the socket 400 will now be described. The housing420 includes a first body 320 and a second body 340. The first andsecond bodies 320 and 340 can be detachably coupled together. The firstbody 320 is fixed to the test unit 100, and the second body 340 is fixedto the handler 200. A support 240 is mounted on the test unit 100 forfixing the first body 320 to the test unit 100. The support 240 has arectangular shape with a central opening. Therefore, the first body 320can be fixed to the test unit 100 through the opening of the support240. A recess 328 is formed in a top center portion of the first body320 for receiving the test object 10. In addition, a plurality of firstholes 322 is formed in the first body 320. The first holes 322 penetratethe first body 320 from a bottom surface of the recess 328 to a bottomsurface of the first body 320. The first holes 322 are aligned with thefirst pads 122 of the test board 120 and the first connection terminals14 of the test object 10 disposed in the recess 328. The first pins 330are inserted in the first holes 322.

The socket substrate 360 is disposed between the second body 340 and thehandler 200. The socket substrate 360 and the second body 340 are fixedto the handler 200 using fasteners (not shown), such as screws.

A plurality of second holes 342 are formed in the second body 340. Thesecond holes 342 are formed through the second body 340 in a verticaldirection from a top surface of the second body 340 to a bottom surfaceof the second body 340. The second holes 342 are aligned with the firstpads 362 of the socket substrate 360 and the second connection terminals16 of the test object 10 disposed in the recess 328 of the first body320. The second pins 350 are inserted in the second holes 342. Vacuumholes 202 are formed through center portions of the socket substrate 360and the second body 340 to allow the handler 200 to create a vacuum forholding the test object 10. As shown in FIGS. 2 and 3, a recess 348 canbe formed in the top surface of the second body 340 for receiving thereference electronic device 380 mounted on the socket substrate 360.Alternatively, the reference electronic device 380 can be disposedoutside the second body 340 by forming the socket substrate 360 widerthan the second body 340 and mounting the reference electronic device380 on a peripheral portion of the socket substrate 360.

In this embodiment, the reference electronic device 380 is directly incontact with the second pads 364 of the socket substrate 360. However,the reference electronic device 380 can be electrically connected to thesecond pads 364 of the socket substrate 360 through, for example, pogopins (not shown).

The second body 340 needs to be accurately coupled to the first body 320for reliable electric contact between the test object 10 and the firstpins 330. For this, alignment pins 344 protrude downward from the bottomsurface of the second body 340, and alignment holes 324 are formed inthe top surface of the first body 320 for receiving the alignment pins344. Alternatively, the alignment pins 344 can be formed on the topsurface of the first body 320, and the alignment holes 324 can be formedin the bottom surface of the second body 340. In addition, alignmentpins 220 protrude downward from a bottom surface of the handler 200, andalignment holes 242 are formed in a top surface of the support 240.Alternatively, the alignment pins 220 can be formed on the top surfaceof the support 240, and the alignment holes 242 can be formed in thebottom surface of the handler 200. This alignment pin/hole structure canbe formed only at the first and second bodies 320 and 340, or thesupport 240 and the handler 200.

In FIGS. 2 and 3, the recess 328 is formed in the first body 320 toreceive the test object 10. Alternatively, the recess 328 can be formedin the bottom surface of the second body 340 for receiving the testobject 10 as shown in FIG. 4.

In the above-described first embodiment, the test object 10 includes asemiconductor device having a logic chip; the reference electronicdevice 380 includes a semiconductor device having a memory chip; and thetest object 10 exchanges electric signals with the reference electronicdevice 380. Alternatively, both the test object 10 and the referenceelectronic device 380 can be semiconductor devices having memory chips.In such a case, interconnection lines can be formed on the test object10 for connecting the first connection terminals 14 directly to thesecond connection terminals 16.

In the first embodiment, the electric connection states of the firstconnection terminals 14 formed on the bottom surface of the test object10 can be measured simultaneously with the electric connection states ofthe second connection terminals 16 formed on the top surface of the testobject 10. Furthermore, before the test object 10 (i.e., the firstsemiconductor device package 10) and the semiconductor device package 20are vertically coupled using the solder balls 30, the test object 10 canbe tested under conditions similar to those of the case where the testobject 10 and the semiconductor device package 20 are verticallycoupled. In addition, if the test object 10 is a semiconductor devicepackage in which a semiconductor device having a logic chip is packaged,it is possible to perform an “at speed test” by including a memory chipin the socket 400.

FIG. 5 is an exploded cross-sectional view illustrating anotherembodiment of a test apparatus 3 according to another aspect of thepresent invention, and FIG. 6 is a cross-sectional view illustrating thetest apparatus 3 assembled for testing the test object 10.

Referring to FIGS. 5 and 6, the test apparatus 3 includes a test unit100, a handler 200, and a socket 400 a. The test unit 100 applies asignal to the test object 10 and receives a signal output from the testobject 10 in response to the input signal. The test unit 100 evaluatesthe state of the test object 10 using the signal output from the testobject 10. The test unit 100 includes a test board 120. First pads 122and second pads 124 are formed on the test board 120. The first pads 122can be used to apply signals to the test object 10, and the second pads124 can be used to receive signals from the test object 10. The socket400 a electrically connects the test object 10 and the test board 120.The handler 200 is used to move the test object 10 to the socket 400 a.The test unit 100 and the handler 200 have typical structures. Thus,detailed descriptions of the test unit 100 and handler 200 will beomitted. The socket 400 a is a characteristic element of the testapparatus 3. In the following description, the socket 400 a will bemainly described in detail, and features of the test unit 100 andhandler 200 different from typical structures will be described.

The socket 400 a includes a housing 420 a, a first connection unit 440,and a second connection unit 460 a. The housing 420 a is disposedbetween the handler 200 and the test board 120 for receiving the testobject 10 during a test operation. The first connection unit 440 is usedto evaluate electrical connection states of the first connectionterminals 14 of the test object 10. The second connection unit 460 a isused to evaluate electrical connection states of the connectionterminals 16 of the test object 10.

The first connection unit 440 includes a plurality of first pins 330 forelectrically connecting the first connection terminals 14 of the testobject 10 directly to the first pads 122 of the test board 120. Pogopins having elastic cores (not shown) can be used as the first pins 330.Ends of the first pins 330 are brought into contact with the firstconnection terminals 14 of the test object 10, respectively, and theother ends of the first pins 330 are brought into contact with the firstpads 122 of the test board 120, respectively.

The second connection unit 460 a includes a socket substrate 360, secondpins 350, and third pins 380 a. The socket substrate 360 includes firstpads 362 and second pads 364. Interconnection lines (not shown) areformed on the socket substrate 360 for electrically connecting the firstpads 362 and the second pads 364. The second pins 350 of the secondconnection unit 460 are used for electrically connecting the first pads362 of the socket substrate 360 directly to the connection terminals 16of the test object 10. Pogo pins having elastic cores (not shown) can beused as the second pins 350. Ends of the second pins 350 are broughtinto contact with the connection terminals 16 of the test object 10,respectively, and the other ends of the second pins 350 are brought intocontact with the first pads 362 of the socket substrate 360,respectively. The third pins 380 a are used for electrically connectingthe second pads 364 of the socket substrate 360 directly to the secondpads 124 of the test board 120. Ends of the third pins 380 a are broughtinto contact with the second pads 364 of the socket substrate 360,respectively, and the other ends of the third pins 380 a are broughtinto contact with the second pads 124 of the test board 120,respectively.

Electrical connection states of the first and second connectionterminals 14 and 16 of the test object 10 can be tested as follows. Asan example, a signal output from the test board 120 is transmitted tothe socket substrate 360 through the first pins 330, the firstconnection terminals 14 of the test object 10, the first semiconductordevice 12 of the test object 10, the second connection terminals 16, andthe second pins 350. Then, the signal is transmitted from the socketsubstrate 360 back to the test board 120 through the third pins 380 a.The test unit 100 evaluates connection states and other electriccharacteristics of the first and second connection terminals 14 and 16of the test object 10 using the returned signal.

Exemplary elements of the socket 400 a will now be described. Thehousing 420 a includes a first body 320 and a second body 340. The firstand second bodies 320 and 340 can be detachably coupled together. Thefirst body 320 is fixed to the test unit 100, and the second body 340 isfixed to the handler 200. A support 240 is mounted on the test unit 100for fixing the first body 320 to the test unit 100. The support 240 hasa rectangular shape with a central opening. Therefore, the first body320 can be fixed to the test unit 100 through the opening of the support240. A recess 328 is formed in a top center portion of the first body320 for receiving the test object 10. In addition, a plurality of firstholes 322 is formed in the first body 320. The first holes 322 penetratethe first body 320 from a bottom surface of the recess 328 to a bottomsurface of the first body 320. The first holes 322 are aligned with thefirst pads 122 of the test board 120 and the first connection terminals14 of the test object 10 disposed in the recess 328. The first pins 330are inserted in the first holes 322. Third holes 326 are formed throughthe first body 320 outside the recess 328. The third holes 326 arevertically formed through the first body 320 from the bottom surface tothe top surface of the first body 320. The third holes 326 are alignedwith the second pads 364 of the socket substrate 360 and the second pads124 of the test board 120. The third pins 380 a are inserted in thethird holes 326.

The socket substrate 360 is disposed between the second body 340 and thehandler 200. The socket substrate 360 and the second body 340 are fixedto the handler 200 using fasteners (not shown), such as screws.

After the first body 320 and the second body 340 are coupled together,the second body 340 is disposed in the recess 328 of the first body 320,and the top surfaces of the first body 320 and the second body 340 areplaced approximately on the same horizontal plane. A plurality of secondholes 342 is formed in the second body 340. The second holes 342 areformed through the second body 340 in a vertical direction from the topsurface of the second body 340 to the bottom surface of the second body340. The second holes 342 are aligned with the first pads 362 of thesocket substrate 360 and the second connection terminals 16 of the testobject 10 disposed in the recess 328 of the first body 320. The secondpins 350 are inserted in the second holes 342. Vacuum holes 202 areformed through center portions of the socket substrate 360 and thesecond body 340 to allow the handler 200 to create a vacuum for holdingthe test object 10.

In this embodiment, the second body 340 is preferably accurately coupledto the first body 320 for reliable electric contact between the testobject 10 and the first pins 330, and the socket substrate 360 and thethird pins 380 a. For this, alignment pins 344 protrude downward fromthe bottom surface of the second body 340, and alignment holes 324 areformed in a bottom surface of the recess 328 of the first body 320 forreceiving the alignment pins 344. Alternatively, the alignment pins 344can be formed on the first body 320, and the alignment holes 324 can beformed in the second body 340. In addition, alignment pins 220 protrudedownward from a bottom surface of the handler 200, and alignment holes242 are formed in a top surface of the support 240. Alternatively, thealignment pins 220 can be formed on the support 240, and the alignmentholes 242 can be formed in the handler 200. This alignment pin/holestructure can be formed only at the first and second bodies 320 and 340,or the support 240 and the handler 200.

In FIGS. 5 and 6, the recess 328 is formed in the first body 320 toreceive the test object 10. Alternatively, the recess 328 can be formedin the bottom surface of the second body 340 for receiving the testobject 10 as shown in FIG. 7. In this case, when assembled, the bottomsurfaces of the first body 320 and the second body 340 can be placed onthe same horizontal plane. In addition, the third holes 326 can beformed in the second body 340 outside the recess 328.

In the second embodiment, the electric connection states of the firstconnection terminals 14 formed on the bottom surface of the test object10 can be measured simultaneously with the electric connection states ofthe second connection terminals 16 formed on the top surface of the testobject 10.

According to aspects of the present invention, the connection states ofthe connection terminals disposed on the bottom surface of the testobject can be tested simultaneously with the connection states of theconnection terminals disposed on the top surface of the test object.

In addition, before the first and second semiconductor device packagesare coupled together using solder balls, the first and secondsemiconductor device packages can be tested under conditions similar tothose in a case where the first and second semiconductor device packagesare coupled together.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover allmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the present invention. Thus, to the maximumextent allowed by law, the scope of the present invention is to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing detailed description.

1. A method of testing electric characteristics of a test objectincluding first connection terminals on a bottom surface and secondconnection terminals on a top surface, the method comprising: providinga socket and loading the test object in the socket, the sockethavingfirst pins electrically contacting the first connection terminals of thetest object and second pins electrically contacting the secondconnection terminals of the test object; and applying an electric signalfrom a test board to the first pins to simultaneously test electriccharacteristics of the first and second connection terminals of the testobject.
 2. The method of claim 1, further comprising: electricallyconnecting the second pins of the socket to an electronic device using asocket substrate that allows the electronic device to exchange electricsignals with the test object, including transmitting the electric signaloutput from the test board back to the test board through the firstpins, the test object, the second pins, the socket substrate, theelectronic device, the socket substrate, the second pins, the testobject, and the first pins.
 3. The method of claim 2, wherein the testobject is a semiconductor device package in which a first semiconductordevice is packaged, and the electronic device comprises a secondsemiconductor device exchanging electric signals with the firstsemiconductor device.
 4. The method of claim 2, wherein the test objectis a first semiconductor device package in which a first semiconductordevice is packaged, and the electronic device comprises a secondsemiconductor device of a second semiconductor device package to bestacked on the first semiconductor device package.
 5. The method ofclaim 4, wherein the first semiconductor device comprises a logic chip,and the second semiconductor device comprises a memory chip.
 6. Themethod of claim 1, further comprising: providing third pins contactingthe test board, and a socket substrate electrically connecting thesecond pins and the third pins, including transmitting the electricsignal output from the test board back to the test board through thefirst pins, the test object, the second pins, the socket substrate, andthe third pins.
 7. The method of claim 6, wherein the test object is asemiconductor device package.
 8. The method of claim 6, wherein the testobject is one of a plurality of semiconductor device packages includedin a multi-chip semiconductor device package.